Moore's law has been the most powerful driver for the development of the microelectronic industry. This law emphasizes lithography scaling and conventional two-dimensional integration of all functions on a single chip, often called system-on-chip (SoC). On the other hand, the integration of all system components can be achieved through system-in-package (SiP) and, ultimately, through three-dimensional IC integration and packaging.
A system-in-a-package includes a number of integrated circuits enclosed in a single package or module. The SiP performs all or most of the functions of an electronic system, and is typically used inside a mobile phone, digital music player, etc. In a SiP, individual integrated circuits can be stacked vertically or arranged horizontally. They are internally connected by fine wires that are bonded to the package. Alternatively, with a flip-chip technology, solder bumps are used to join stacked chips together.
Another solution for improving the integration of the circuit component is three-dimensional integrated circuit (3D IC), which includes two or more layers of active electronic components integrated both vertically and horizontally into a single circuit. Unlike SiP, a 3D IC circuit connects stacked silicon dies with conductors, commonly called Through Silicon Vias (TSVs), running through the die. TSV plays a very important role in modern 3D IC integration and packaging. It can be used for stacking up a series of memory chips and provides a signal or heat path between the chips. Also, it can be used in an interposer or substrate to support fine-pitch, high-power, and high-density integrated circuit (IC) chips.
In “Fabrication and characterization of robust through-silicon vias for silicon-carrier applications,” IBM Journal of Research and Development, Vol. 52,No. 6,pp. 571-581, 2008, Andry et al. laid open a schematic representation of die stacking with TSV and integrated passive functions. In there, the TSV carrier has back-end-of-line (BEOL) redistribution layers and its top-side is used to support the chips with micro-bumps. The bottom-side of the TSV interposer is attached to simple organic/ceramic substrates.
In “Development of Through Silicon Via (TSV) interposer technology for large die (21×21 mm) fine-pitch Cu/low-k FCBGA packet,” in Proceedings of 59th Electronic Components and Technology Conference, pp. 305-312, 2009, Zhang et al. describes a high-performance 65 nm Cu/low-k large chip supported by and attached to the bottom side of a TSV interposer.
In U.S. Pat. No. 6,846,725, Nagarajan et al. laid open a scheme for micro-electro-mechanical system (MEMS) packaging with TSV. In there, the MEMS device on a silicon substrate is protected by a cap with TSV for vertical electrical feed-through. For 3D MEMS packaging, the TSV cap can be an ASIC chip with TSV.
As Moore predicted in 1965, silicon chips are getting larger while incorporating a higher pin count and finer pad pitch. Unfortunately, conventional substrates with build-up layers made up of organic materials, e.g., bismaleimide triazine (BT), are facing great challenges in supporting these high pin-count, fine-pitched silicon chips. Thus, to address these needs, silicon interposer with high-density TSV has emerged as a perfect solution to provide high wiring density redistribution and interconnection.
In conventional face-down plastic ball grid array (PBGA) packages, the chip is supported by the high-density BT-substrate with build-up layers. As the chip gets bigger with a higher pin count and finer pitch, the BT substrate can no longer support it. Hence there is a need for an intermediate substrate (e.g., the TSV interposer) to redistribute the large array of fine-pitch pads on the chip to fewer and relatively larger pitch pads on a simpler and thinner BT substrate even without any build-up layers. The foot-print of this TSV package is much smaller than those with high-density BT-substrate with build-up layers.
Generic 3D IC integration technology for high-performance computing systems provides TSVs in 3D chip stacks or in a chip carrier, thereby enabling the very high-power, high pin-count, and fine-pitch active components and memory chips stacked together in a 3D structure.
However, due to high density and high complexity of the circuit components, it is difficult to dispose TSV on the active circuit dies and wafers. In addition, the chip size and number of pin outs on the circuit components are unlikely the same. Therefore, forcing them together will reduce design flexibility and compromise the functionalities. In addition, electrical performance is usually compromised due to the longer routings in these circuits.
Another critical issue of 3D IC integrations is thermal management. In conventional 3D ICs, the 3D structure causes increased total power generation per unit substrate area. Individual chip in the 3D stack may be overheated if cooling is not properly and adequately provided, The space between individual chips in the 3D stack may be too small for providing cooling channels due to the fact that gaps are too small for fluid flows.
Finally and more importantly, the requirement of TSV manufacturing yield is too high (normally greater than 99.99%) for the TSV components in order to justify the addition of costs due to the TSV yield loss.
For the reasons discussed above, low-cost and effective thermal management solutions are highly desired for widespread use of high-performance 3D IC integration devices.